1. Kausik Majumdar, Kota V. R. M. Murali, Navakanta Bhat, and Yu-Ming Lin “External Bias Dependent Direct To Indirect Band Gap Transition in Graphene Nanoribbon” Nanoletters (Available online)
2. Kausik Majumdar, Navakanta Bhat, Prashant Majhi, and Raj Jammy, “Effects of Parasitics and Interface Traps on Ballistic Nanowire FET in the Ultimate Quantum Capacitance Limit”, IEEE Transactions on Electron Devices (Available online)
3. K. Majumdar, N. Bhat, P. Mhaji, R. Jammy, ”HFinFET: A Scalable, High Performance, Low Leakage Hybrid N-Channel FET ” IEEE Transactions on Nanotechnology, May 2010
4. V. T. Arun, K N Bhat, N. Bhat, M.S. Hegde, “Fermi level de-pinning at the germanium schottky interface through sulfur passivation”, Applied Physics Letters, April 2010
5. Kausik Majumdar, Kota V.R.M.Murali, Navakanta Bhat and Yu-Ming Lin, “Intrinsic limits of subthreshold slope in biased bilayer graphene transistor”, Applied Physics Letters, Vol.96, 123504, doi:10.1063/1.3364142, 2010.
6. Jayaraman, B., Singh, V. R., Asundi, A., Bhat, N., and Hegde, G. M. ‘‘Thermomechanical characterization of surface-micromachined microheaters using in-line digital holography”, Measurement Science & Technology, IOP, Vol. 21, 015301 (10pp), 2010.
7. R. G. D. Jeyasingh, N. Bhat, B. Amrutur, ”Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique ” , IEEE Transactions on VLSI Systems, November 2009 (Available online)
8. Ajayan K.R., Navakanta Bhat, “Linear transconductor with flipped voltage follower in 130 nm CMOS”, Analog Integr Circ Signal Processing, Kluwer, 13 October 2009
9. Balaji Jayaraman, Navakanta Bhat and Rudra Pratap, "Thermal characterization of microheaters from the dynamic response," Journal of Micromechanics and Micoengineering, Vol. 19, 085006 (11pp), 2009.
10.S. Bagga, N.Bhat and S.Mohan, ‘‘LPG Gas-Sensing System With SnO2 Thin-Film Transducer and 0.7-mu m CMOS Signal Conditioning ASIC”, IEEE Transactions on Instrumentation and Measurement 58: 3653-3658, 2009.
11.Balaji Jayaraman, Navakanta Bhat and Rudra Pratap, "Thermal analysis of microheaters using mechanical dynamic response," International Journal of Micro and Nano systems, 1(1), pp. 15 – 20, 2009.
12.B. Jayaraman and Navakant Bhat, “Performance analysis of subthreshold cascode current mirror in 130nm CMOS technology,” J. Low Power Electronics, Vol. 5, No. 4, pp. 484 – 496, Dec. 2009
13.Santosh Hegde, Thejas, Navakanta Bhat, “Universal Capacitance Sensor”, International J. of Micro and Nano Systems, 1(1),2009,pp.21-27, 2009.
14.B. P. Harish, Navakanta Bhat, and Mahesh B. Patil, “Hybrid-CV Modeling for Estimating the Variability in Dynamic Power” J. Low Power Electronics ASP 4, 263–274 December (2008)
15.K. Majumdar, N.Bhat, “Bandstructure Effects in Ultra-Thin-Body Double-Gate Field Effect Transistor: A Fullband Analysis” Journal of Applied Physics, Volume 103, Issue 11, pp. 114503-114503-9 (2008).
16.R. Srinivasan and Navakanta Bhat, “Optimisation of Gate-Drain/Source Overlap in 90 nm NMOSFETs for Low Noise Amplifier Performance” J. Low Power Electronics, ASP 4, 240-246 August (2008)
18.M.P. Singh, K. Shalini, S.A.
19.B.P. Harish, Navakanta Bhat, and Mahesh B. Patil, “On A Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 26(3):pp. 606-614, 2007
20.N. Bhat, “Nanoelectronics Era : Novel Device Technologies Enabling Systems on Chip”, J. Indian Institute of Science, vol. 87: 1, Jan-Mar 2007, pp. 61-74
21.G. Krishnan, C. U. Kshirasagar, G.K.Ananthasuresh, N. Bhat, “Micromachined High-Resolution Accelerometers”, J. Indian Institute of Science, vol. 87: 3, Jul-Sept 2007
22.B.P. Harish, Navakanta Bhat, and Mahesh B. Patil, “Analytical modeling of CMOS circuit delay distribution due to concurrent variations in multiple processes”, Solid State Electronics, Vol. 50, pp 1252-1260, (2006).
23.M. P. Singh, K. Shalini, and S. A.
24.R. Sreenivasan and N. Bhat, “Effect of Gate-Drain/Source Overlap on the noise in 90nm NMOSFETs” Journal of Applied Physic, 2006
8. R Srinivasan and Navakanta Bhat,
“Scaling Characteristics of fNQS and ft in NMOSFETs with Uniform and
Non-uniform Channel Doping”, International
Journal of Electronics, Taylor and Francis
9. R Srinivasan and NavakantaBhat, “Scaling Characteristics of fNQS and ft in NMOSFETs with and without Supply Voltage Scaling”, Jl. of Indian Institute of Science, Vol 85, Aug 2005.
10.A. Gupta and N. Bhat, “On the Performance Analysis of a Class of Neuron Circuits”, Analog Integrated Circuits and Signal Processing, Kluwer 44 (3), pp. 293-302, September 2005
11.C. Venkatesh, S. Pati, N. Bhat and R. Pratap, “A Torsional MEMS Varactor with Wide Dynamic Range and Low Actuation Voltage”, Sensors and Actuators A Physical, June 2005
12.H.C. Srinivasaiah and N. Bhat, “Characterization of Sub-100nm CMOS Process Using Screening Experiment Technique”, Solid State Electronics, Vol. 49, pp 431-436, (2005)
30.A. Gupta and N. Bhat, “Asymmetric Cross-Coupled Differential Pair Configuration to Realize Neuron Activation Function and its Derivative”, IEEE Transactions on Circuits and Systems Part II: Express Briefs, Vol. 52, No. 1, pp. 10-13, January 2005
31.M.P. Singh, C.S. Thakur, K. Shalini, S. Banerjee, N. Bhat, and S.A. Shivashankar, “Structural, Optical, and Electrical Characterization of Gadolinium Oxide Films Deposited by Low-pressure Metalorganic Chemical Vapour Deposition”, Journal of Applied Physic, Vol 96, No. 10, pp. 5631-5637, 15 November 2004
32.A. Gupta and N. Bhat, “Back-Gate Effect to Generate Derivative of Neuron Activation Function”, Analog Integrated Circuits and Signal Processing, Kluwer 41 (1), pp. 89-92, October 2004
33.R. Singh and N. Bhat, “An Offset Compensation Technique for Latch Type Sense Amplifier in High Speed Low Power SRAMs”, IEEE Transactions on VLSI Systems, June 2004, pp. 652-657
34.K. Maitra and N. Bhat, “Impact of Gate to Source/Drain Overlap Length on 80 nm CMOS Circuit Performance”, IEEE Transactions on Electron Devices, March 2004 pp.409-414.
35.N. Bhat, “MEMS for RF Applications”, IETE Technical Review, vol. 21, no. 2, March-April 2004.
36.N. Bhat and C.S.Thakur, “Analog CMOS Performance Degradation due to Edge Direct Tunneling (EDT) Current in sub-100nm Technology” invited paper for Journal of Semiconductor Technology and Science special issue on Device Reliability, September 2003
37.M.P. Singh, C.S. Thakur, K. Shalini, N. Bhat, and S.A. Shivashankar, “Structural and Electrical Characterization of Erbium Oxide Films Grown on Si(100) by Low-pressure Metalorganic Chemical Vapour Deposition”, Applied Physics Letters, October 2003.
38.H C Srinivasaiah and N. Bhat, “Monte Carlo Analysis of the Implant Dose Sensitivity in 0.1 mm NMOSFET”, Solid-State Electronics, 47/8 pp. 1379-1383, August 2003
39.H C Srinivasaiah and N. Bhat, “Mixed Mode Simulation Approach to Characterize the Circuit Delay Sensitivity to Implant Dose Variations”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 22 , no. 6, pp. 742-747, June 2003
40.P.K.Saxena and N.Bhat, “Process technique for SEU reliability improvement of deep sub-micron SRAM cell”, Solid-State Electronics, Vol. 47, 4, April 2003, pp. 661-664.
41.P.K.Saxena and N.Bhat, “SEU Reliability Improvement Due to Source-Side Charge Collection in the Deep-Submicron SRAM Cell”, IEEE Transactions on Device and Material Reliability, pp.14-17 March 2003.
42.K. Maitra and N. Bhat, “Polyreoxidation process step for suppressing edge direct tunneling through ultrathin gate oxides in NMOSFETs”, Solid-State Electronics, Vol. 47, 1, January 2003, p. 15-17
43.K. Maitra and N. Bhat, “Analytical approach to integrate the different components of direct tunneling current through ultrathin gate oxides in n-channel metal oxide semiconductor field-effect transistors”, Journal of Applied Physics, Vol 93, No. 2, pp. 1064-1068, 15 January 2003.
44.N. Bhat, A. Wang and K.C. Saraswat, “Rapid thermal anneal of gate oxides for low thermal budget TFTs,” IEEE Transactions on Electron Devices , p.63, January 1999.
45.N. Bhat, and K.C.Saraswat, “Characterization of border trap generation in rapid thermally annealed oxides deposited using silane chemistry”, Journal of Applied Physics , p. 2722, September 1998
46.N. Bhat, M. Cao and K.C. Saraswat, “Bias temperature instability in hydrogenated thin-film transistors,” IEEE Transactions on Electron Devices, p.1102, July 1997
47.N. Bhat, P.P. Apte and K.C. Saraswat, “Charge trap generation in LPCVD oxides under high field stressing,” IEEE Transactions on Electron Devices, p.554, April 1996
48.N. Bhat, and J.Vasi, “Interface-state generation under radiation and high field stressing in reoxidized nitrided oxide MOS capacitors,” IEEE Transactions on Nuclear Science, p.2230, Dec. 1992