Conference Publications 

 

1.    AdityaSankar Medury,  Navakanta Bhat and K.N.Bhat, “A Compact Model incorporating Quantum Effects for Ultra-Thin-Body Double-Gate MOSFETs" International Nanoelectronics Conference (INEC), Jan 2010

2.  Sindhuja Sridharan, Navakanta Bhat,, K.N. Bhat, "pSi-ZnO solar cells fabricated by sol gel method" XV International Workshop on the Physics of Semiconductor Devices(IWPSD), Dec 2009

3.  Ajayan K.R., Navakanta Bhat, “Impact of Annealing Temperature on Device Variability” IWPSD, XV International Workshop on the Physics of Semiconductor Devices(IWPSD), Dec 2009

4.  AdityaSankar Medury, Navakanta Bhat and K.N.Bhat "Ultra-Thin-Body Symmetric Double-Gate MOSFETs: A Perturbation Based Device Model Incorporating Quantization Effects", XV International Workshop on the Physics of Semiconductor Devices(IWPSD), Dec 2009

5.  K. Majumdar, M. Kota,  Navakanta Bhat and Y.M. Lin "Self-Consistent Electronic Structure of Graphene Nanoribbon Devices," XV International Workshop on the Physics of Semiconductor Devices(IWPSD), Dec 2009

6.  K. Majumdar and Navakanta Bhat "Effect of Volume Inversion in Ultra-Thin-Body Double Gate FET," XV International Workshop on the Physics of Semiconductor Devices(IWPSD), Dec 2009

7.  B.P. Harish, Navakanta Bhat, and Mahesh B. Patil, “Bridging Technology-CAD and Design-CAD for Variability Aware Nano-CMOS Circuits”, IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 Pages: 2309-2312, 2009

8.  AdityaSankar Medury, Navakanta Bhat and K.N.Bhat "Modeling theThreshold Voltage of Ultra-Thin-Body(UTB) Long Channel Symmetric Double-Gate (DG) MOSFETs" International Semiconductor Device Research Symposium(ISDRS), Dec 2009

9.  S.Khan, Thejas, G.K.Ananthasuresh and Navakant Bhat, “"Design and Characterization of a Micro machined Accelerometer with Mechanical Amplifier for Intrusion Detection", Proc. of ISSS 2009, National Conference on Smart Materials Structures and Systems, 2009

10.Ajayan K.R.,  Navakant Bhat “Impact of Process Variability on 28nm Analog CMOS”  13th IEEE/VSI VLSI Design and Test Symposium July 2009

11.N. Bhat, B. Jayaraman, R. Pratap, S. Bagga, S. Mohan, “Integrated CMOS Gas Sensor System”, Invited talk at the International conference on Electron Devices and Semiconductor Technology (IEDST), 2009

12.C. Malhi, R. Pratap, N. Bhat, "High Sensitivity FET Integrated MEMS Deflection Sensor", IEEE Sensors 2009

13.C. Malhi, R. Pratap and N. Bhat, “Design of a High Sensitivity FET Integrated Microphone", Eurosensors September 2009, Procedia Chemistry, Vol. 1, pp.875-878, 2009

14.G.C. Deepak and Navakanta Bhat, “RF Sputtered Er2O3 Thin Films as High Gate Dielectrics for Germanium MOS Devices, ECS Transactions, 19 (1) , 215th ECS Meeting, San, May 2009

15.V. T. Arun, K. N Bhat and Navakanta Bhat, “Effect of annealing temperature on electrical characteristics of Pt-Ge Schottky junctions”, International Workshop on the Physics of Semiconductor Devices (IWPSD), 2009.

16.Malhi Charanjeet Kaur, Rudra Pratap and Navakanta Bhat, “MOSFET based MEMS Microphone with Wide Frequency Band”, International Conference on MEMS (ICMEMS 2009), IIT Madras, January 3-5, 2009.

17.Thejas, Navakanta Bhat, Rudra Pratap, “High Accuracy Angular RateSensing using GyroFET”, Proc. of ICMEMS 2009, Intl. Conference on MicroElectroMechanical Systems, 2009.

18.C. Venkatesh, N. Bhat, “Design and Characterisation of High Dynamic range Torsional Varactor”, Invited talk at the International Conference on MEMS (ICMEMS), 2009

19.A.V.S.S. Prasad, N. Bhat, “Test Structure Characterization and Fault Modeling of SOI MUMPS Process”, International Conference on MEMS (ICMEMS), 2009

20.S. Ananad, N. Bhat, K. N. Bhat, S. Mohan, “A Surface Modification Process for Lift-off Applications using Direct Write Laser Lithography”, International Conference on MEMS (ICMEMS), 2009

21.Jairam S, Kusum Lata, Subir Roy and   Navakanta Bhat, “Formal Verification of a MEMS based adaptive cruise control system”, Modeling and Simulation of Microsystems, NSTI Nanotech, pp.611-614,  2008

22.Jairam S, Navakanta Bhat, “GyroCompiler:A Soft IP Model Analysis and Synthesis framework for design of MEMS based Gyroscope”, International Conference on VLSI Design 2008.

23.Kusum Lata, Jairam Sukumar, Subir Roy , Jamadagni H S, Navakanta Bhat, “Case Studies Towards a Platform Independent Framework for Formal Verification of Hybrid Systems”, VDAT 2008.

24.Jairam S, Kusum Lata, Subir Roy and Navakanta Bhat, Verification of a MEMS Based Adaptive Cruise Control using Simulation and Semi-Formal Approaches”, International Conference on Electronic Circuits and Systems (ICECS) 2008.

25.S.A. Kannan, Satyam Dwivedi, Manodipan Sahoo Bharadwaj Amrutur and Navakanta Bhat, “Optimal power and noise allocation for analog and digital sections of a low power radio receiver”, IEEE ISLPED 2008.

26.Vedavathi S., Jayashree K. P., K. Navakanta Bhat, K N  Bhat, S. Mohan, “Studies on KOH anisotropic etching for MEMS applications”, Proceedings of International Conference on Emerging Microelectronics and Interconnection Technology (EMIT-08), December 15-18, 2008.

27.Siva Rama Krishna Vanjari, Navakanta Bhat, Bharadwaj Amrutur and Sampath Srinivasan, "Micromachined electrochemical cell platform for biosensors," International Conference on Smart Materials, Structures and Systems (ISSS), 2008

28.Santosh Hegde, Thejas and Navakanta Bhat, "Universal capacitance sensor," International Conference on Smart Materials, Structures and Systems (ISSS), 2008.

29.Balaji Jayaraman, Navakanta Bhat and Rudra Pratap, "Thermal analysis of microheaters using mechanical dynamic response," International Conference on Smart Materials, Structures and Systems (ISSS), 2008.

30.Rakesh Gnana David J and Navakanta Bhat, "A low power, process invariant keeper design for high speed dynamic logic circuits", ISCAS 2008.

31.Sen, Srimoyee; Roy, Urmimala; Kshirsagar, Chaitanya; Bhat, Navakanta; Sarkar, Chandan Kumar, “Circuit prospects of DGFET: Variable gain differential amplifier an a schmitt trigger with adjustable hysteresis”, Very Large Scale Integration, 2007. VLSI - SoC 2007. IFIP International Conference on, Volume , Issue , 15-17 Oct. 2007 Page(s):280 - 283

32.N. Bhat and C. Venkatesh, “Impact of Beam Dimensions on Torsional Varactor”, Invited paper at International Conference on Advanced Materials (ICAM), IUMRS 2007

33.P.R.Kumar, C.Venkatesh, R.Pratap and N. Bhat, “C-V Characterization of a MEMS Torsional Varactor”, International Conference on Advanced Materials (ICAM), IUMRS 2007

34.Harish, BP, Bhat, Navakanta and Patil, Mahesh B, "Process Variation Aware Estimation of Static Leakage Power in Nano-CMOS", SISPAD 2007.

35.Satyam Dwivedi, Bharadwaj Amrutur, Navakanta Bhat, "Optimizing Resolution of Signals in a Low IF Receiver", IEEE ISSCS 2007.

36.Harish, BP and Bhat, Navakanta and Patil, Mahesh B, " CV based Analytical Modeling of Dynamic Power for 65-nm CMOS Library Characterization", IEEE VLSI Design and Test Symposium 2007.

37.Harish, BP and Bhat, Navakanta and Patil, Mahesh B, "Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs", International Conference on Computing: Theory and Applications, 2007.

38.G.C. Deepak, Navakanta Bhat, and S.A. Shivashankar, "Structural and Electrical Properties of Er2O3 Thin Films Deposited by RF Sputtering for Gate Dielectric Applications", E1-0586, 211th ECS Meeting, Chicago, May 2007

39.C.Venkatesh and Navakanta Bhat, "Reliability of torsional varactor", International Symposium on physical and failure analysis of Integrated Circuits, July 2007.

40.Balaji Jayaraman and Navakanta Bhat, “High precision 16-bit readout gas sensor interface in 0.13ěm CMOS,” International Symposium on Circuits and Systems, pp. 3071 – 3074, May 2007

41.K. Sivaramakrishna, K. Jayant and N. Bhat, “A Novel CMOS Compatible Three Terminal 3D Tunable Micro Inductor”, IEEE VLSI Design and Test Symposium, 2006

42.S. Jayaram and N. Bhat, “Integrated Stability Analysis Methods for Hybrid Systems”, IEEE VLSI Design and Test Symposium, 2006

43.S. Bagga, N. Bhat and S. Mohan, “Gas Sensor Interface ASIC on 0.7mm CMOS Technology”, IEEE VLSI Design and Test Symposium, 2006

44.K. Sandeep, C. Kshirasagar and N. Bhat, “General Purpose Capacitive Sensing Circuit using Correlated Double sampling”, IEEE VLSI Design and Test Symposium, 2006

45.Balaji Jayaraman and Navakanta Bhat, “System Level Modeling and Simulation of a Gas Sensor Interface”, IMAPS India National Conference, 2006

46.B.P. Harish and Navakanta Bhat, “Resistive Modeling of Estimation of Static Leakage Power in Nanoscale CMOS”, IMAPS India National Conference, 2006

47.S.Bagga, S.Mohan and N.Bhat," Effect of the Sensor Film Thickness on the Sensitivity of the Tin Oxide based LPG Gas Sensor" in proceedings of the Conference on Smart Structures and MEMS System for Aerospace Applications, December 1-2,2006, Hyderabad, India.

48.S.Bagga, S.Mohan and N.Bhat," Influence of Substrate Temperature on the Optical and Structure Properties of Tin Oxide Films" in National Symposium on Instrumentation, October 12-15, 2006, Gwalior, India.

49.Balaji Jayaraman and Navakanta Bhat, “A Temperature Independent Current Source on 0.13µm CMOS Technology”, International Conference on Computers and Devices for Communication (CODEC), 2006

50.K. Jayant, Hithesh Gatty and Navakanta Bhat, “A novel low actuation Voltage switch using the concept of displacement amplification”, Indo-Chinese Workshop on MEMS, 2006

51.C. Kshirasagar, A. Madan, N.Bhat, “Device Performance Variations in 20nm Trigate FinFET”, International Workshop on Physics of Semiconductor Devices, December 2005

52.C. Venkatesh, K.J.Vinoy and N. Bhat, “Application of Torsional Varactor in the design of phase shifters” International Conference on MEMS and Semiconductor Nanotechnology, IIT Kharagpur, December 2005

53.N. Bhat, S. Rajesh, S. Syamala, “ASIC Interface design for MEMS Gyroscope Sensor”, Invited paper at the National Symposium on Instrumentation, CUSAT, Cochin, November 2005

54.C. Venkatesh, and N. Bhat, “Issues in design of torsional MEMS varactor”, Invited paper at ISSS Conference, Bangalore, July 2005.

55.S. Rajesh, S. Syamala, N. Bhat, “Novel Test Structure to Emulate Capacitance Variations of a Rate-Grade Gyroscope”. Asian Solid State Circuits Conference, Taiwan, November 2005

56.N. Bhat, “SOC Technology : CMOS and Beyond”, Invited tutorial at the Asia South Pacific International Conference on Embedded Systems”, July 2005

57.B.P. Harish, Navakanta Bhat, and Mahesh B. Patil, “Modeling of the effects of process variations on circuit delay at 65nm”, IEEE CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, PROCEEDINGS pp.  761-764 ,  2005

58.R. Srinivasan and N. Bhat, “Impact of channel engineering on unity gain frequency and noise figure in 90nm NMOS transistor for RF application”, 18th International VLSI Design Conference, Calcutta , January 2005.

59.R. Srinivasan and N. Bhat, “Impact of Gate-Drain/Source Overlap on Noise Figure in 90nm NMOS Transistor for RF Applications”, International Symposium on Microwaves, 2004

60.B.P.Harish, N. Bhat, “Characterization of 65nm CMOS NAND gate delay sensitivity on gate length and implant dose variations”, IINC 2004

61.J.P.Kulkarni, N.Bhat, “Process technique for improving the tuning range in MOS varactor”, Proceedings of the IEEE INDICON, pp. 534-537, 2004.

62.J.P.Kulkarni, N.Bhat, “Improving Tuning Range in Varactors using Poly-Silicon depletion Effect”, Asia Pacific Microwave Conference, New Delhi, 2004.

63.C. Venkatesh and N. Bhat, “A MEMS Oscillator based on Displacement Sensing Principle”, 8th IEEE VLSI Design and Test Workshops 2004

64.B.P.Harish, R.Srinivasan and N. Bhat, “Process Sensitivity Evaluation of 90nm CMOS Technology with Gate to Source/Drain Overlap Length as a Device Design Parameter”, 8th IEEE VLSI Design and Test Workshops 2004

65.R. Sangati, S. Syamala and N. Bhat, “Capacitance Sensing Techniques for MEMS Gyroscope”, 8th IEEE VLSI Design and Test Workshops 2004

66.R. Srinivasan and N. Bhat, “Reassessment of Channel Engineering in sub-100nm MOSFETs”, 8th IEEE VLSI Design and Test Workshops 2004

67.H C Srinivasaiah and N. Bhat, “Response Surface Modeling of 100nm CMOS Process Technology Using Design of Experiment”", 17th International VLSI Design Conference, 2004, Bombay

68.S Jairam, N. Bhat, S. S. Bisht, R. Pratap,  “A Quasi Static Model for a Simply Supported Beam in a Circuit Simulation Framework”, 17th International VLSI Design Conference, 2004, Bombay

69.M. P.Singh, C.S.Thakur, K.Shalini, T. Shripathi, N. Bhat and S.A.Shivashankar, “ A Comparative Study of Erbium Oxide and Gadolinium Oxide High-K Dielectric Thin Films Grown by Low Pressure Metalorganic Chemical Vapour Deposition (MOCVD) Using b-Diketonates as Precursors”, 204th Meeting of Electrochemical Society, USA, 2004

70.M.P.Singh, G.C.Deepak, N. Bhat and S.A.Shivashankar, “Electrical Characterization of Gd2O3  Deposited by Low Pressure Metalorganic Chemical Vapour Deposition” INAE Conference on Nanotechnology, Chandigarh,  December 2003

71.N. Bhat and S. Pamidighantam, “MEMS and Applications”, Tutorial at IEEE TENCON 2003, October 2003, Bangalore

72.G.C.Deepak, M.S.Dharmapraksh, N. Bhat and S.A.Shivashankar, “Electrical Characterization of MOCVD grown HfO2 Thin Films for Gate Dielectric Applications”, 12th International Workshop on Physics of Semiconductor Devices, Chennai, pp. 456-458, 2003

73.A. K. Pugalia, J.P. Kulkarni, N. Bhargava and N. Bhat, “Single Pocket Halo Sensitivity in 100nm Ananlog Transistor Design”, 12th International Workshop on Physics of Semiconductor Devices, Chennai, pp. 603-605, 2003

74.A. Kumar, R. Pratap and N. Bhat, “Modeling and Simulation of Thermalization Profile of Sputtered Atoms in a Glow Discharge Cell”, 12th International Workshop on Physics of Semiconductor Devices, Chennai, pp. 564-566, 2003

75.N. Bhat, C. Venkatesh and S. Pati, “Micro Electro Mechanical Systems (MEMS): An Overview”, Tutorial at 7th IEEE VLSI Design and Test Workshops 2003, Bangalore

76.A. K. Gupta and N. Bhat, “A Low Power Circuit to Generate Neuron Activation Function and its Derivative using Back Gate Effect”, 7th IEEE VLSI Design and Test Workshops 2003, Bangalore

77.S. Deb and N. Bhat, “Design and Implementation of Passive RF Tag IC”, 7th IEEE VLSI Design and Test Workshops 2003, Bangalore

78.C.S.Thakur and N. Bhat, “Impact of Gate to Source/Drain Overlap for Analog CMOS Circuit Application in sub-100nm Technology”, 7th IEEE VLSI Design and Test Workshops 2003, Bangalore

79.R Srinivasan and N. Bhat, “Effect of Scaling on the Non-Quasi-Static Behaviour of the MOSFET for RF IC's, 16th International VLSI Design Conference 2003, New Delhi

80.M.P. Singh, C.S. Thakur, K. Shalini, N. Bhat and S.A. Shivashankar, “Characterization of a Potential Gate Dielectric: MOCVD Grown Erbium Oxide on Silicon”,  Electro Chemical Society  Conference, Paris,  2003

81.S. Pati, C. Venkatesh, N. Bhat and R. Pratap, “Voltage Controlled Oscillator Using Tunable MEMS Resonator”, 2nd International Conference on Materials for Advanced Technologies, Singapore 2003

82.C. Venkatesh, S. Pati and N. Bhat, “Torsional MEMS Varactor with Low Actuation Voltage” 2nd International Conference on Materials for Advanced Technologies, Singapore 2003

83.M. P. Singh, C. S. Thakur, N. Bhat, and S. A. Shivashankar, “A study of Al2O3:C films on Si(100) grown by low pressure MOCVD”, Material Research Society  fall Meeting USA  2003

84.H. C Srinivasaiah and N. Bhat, “Implant dose sensitivity of 0.1mm CMOS inverter delay", 7th ASPDAC / 15th International VLSI Design Conference, 2002, Bangalore

85.H. C Srinivasaiah and N. Bhat  "Statistical modelling of 0.1mm NMOS device characteristics for implant dose variations", 6th IEEE VLSI Design & Test workshop-2002, Bangalore

86.K. Maitra and N. Bhat, "Poly-reoxidation Process Step for Suppressing Edge Direct Tunneling (EDT) Through Ultrathin Gate Oxides in NMOSFETs", 6th IEEE VLSI Design & Test workshop-2002

87.P. K Saxena and N. Bhat, "Single Event Upset Response of a 0.09mm SRAM cell using 2D and 3D simulation", 6th IEEE VLSI Design & Test workshop-2002, Bangalore

88.R. Srinivasan, C Venkatesh and N. Bhat, "Comparative study of Tuned amplifier performance with different inductor configurations", 6th IEEE VLSI Design & Test workshop-2002, Bangalore

89.A. Gupta and N. Bhat, "Hardware realisation of a digitally controllable neuron activation function and its derivative for extremely low power applications", 6th IEEE VLSI Design & Test workshop-2002

90.N. Bhat, “CMOS Technology Issues in Mixed Signal Design” Invited Tutorial, 6th IEEE VLSI Design & Test workshop-2002, Bangalore

91.H.C. Srinivasaiah and N. Bhat, “Optimization of 0.1mm NMOS Transistor using Disposable Spacer Technique”, 5th IEEE VLSI Design and Test Workshop, 2001

92.Simi E., Sudheer S.S. and  N. Bhat, “Dual Vt Technology using Dual Thickness Gate Oxide”,  5th IEEE VLSI Design and Test Workshop, 2001

93.H. C. Srinivasaiah and N. Bhat, "Simulation Study of Implant Dose Sensitivity of a 0.1 mm NMOSFET", 11th International Workshop on "The Physics  of Semiconductors” 2001

94.N. Bhat, “Circuit and Process Perspectives for the Transistor Design in the Deep Sub-micron Technology”, Invited talk at the National seminar on VLSI: Systems, Design and Technology, 2000

95.Chheda S, Bhat N, Tsui P, Gonzales S, Cave N, Fu CC, Huang F, Nangia A, Choi PSJ, Collins S, “Gate length and threshold voltage dependent non-linearity in the hot carrier DC lifetime extrapolation for sub 100nm NMOS devices”, PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE), vol. 3881, pp.175-185, 1999  

96.N. Bhat, P. Chen, P. Tsui, A. Das, M. Foisy, Y. Shiho, J. Higman, J-Y Nguyen, S. Gonzales, S. Collins, D. Workman, “Hot carrier reliability considerations in the integration of dual gate oxide transistor process on a sub-0.25µm technology for embedded applications,” International Electron Device Meeting, 1998.

97.N. Bhat, H. Chuang, P. Tsui, R. Woodruff, J. Grant, R. Kruth, A. H. Perera, S. Poon, S. Collins, D. Dyer, V. Misra, I. Yang, S. Venkatesan, P. V. Gilbert, “Performance, standby power, and manufacturability trade-off in transistor design consideration for 0.25-µm technology,” SPIE Microelectronics Device Technology conference, 1998

98.Venkatesan S, Gelatos AV, Misra V, Smith B, Islam R, Cope J, Wilson B, Tuttle D, Cardwell R, Anderson S, Angyal M, Bajaj R, Capasso C, Crabtree P, Das S, Farkas J, Filipiak S, Fiordalice B, Freeman M, Gilbert PV, Herrick M, Jain A, Kawasaki H, King C, Klein J, Lii T, Reid K, Saaranen T, Simpson C, Sparks T, Tsui P, Venkatraman R, Watts D, Weitzman EJ, Woodruff R, Yang I, Bhat N, Hamilton G, Yu Y, “A high performance 1.8V, 0.20 mm CMOS technology with copper metallization”, pp. 769-772, INTERNATIONAL ELECTRON DEVICES MEETING – 1997

99.Wang AW, Bhat N, Saraswat KC, “TMCTS for gate dielectric in thin film transistors”, MATERIALS RESEARCH SOCIETY SYMPOSIUM PROCEEDINGS, vol. 424    pp. 281-286, 1997  

100.      N. Bhat, A. Wang and K.C. Saraswat, “Effect of annealing ambient on performance and reliability of LPCVD oxides for TFTs,” Material Research Society  spring meeting, 1996

101.      N. Bhat, M.Cao and K.C.Saraswat, “Bias temperature instability in hydrogenated polysilicon thin film transistors,” Society for Information Display conference ,  1995

102.      N. Bhat and K.C.Saraswat, “Interface-state generation in deposited oxides due to bias temperature stress,” Electrochemical Society extended abstracts, 1994

103.      N. Bhat and K.C.Saraswat, “Degradation of LPCVD oxides,” International Display Research conference, 1994

104.      H. Oi, Y. Shiho, P. Chen, N. Bhat, “Dual Gate Oxide Process Integration for High Performance Embedded Memory Products”,  Solid state Device Meeting, 1998

105.      T.C.Yang, N.Bhat, and K.C. Saraswat, “Effect of interface stress on reliability of gate oxide,” 4th Symposium on Silicon nitride and silicon oxide thin insulating films. 191st meeting of the ECS, May 1997  (invited paper).

106.      Yang TC, Bhat N, Saraswat KC, “Dependence of reliability of ultrathin MOS gate oxides on the Fermi level positions at gate and substrate”, MATERIALS RESEARCH SOCIETY SYMPOSIUM PROCEEDINGS, pp.123-128, 1997

107.      V. Subramanian, N. Bhat, and K.C.Saraswat, “Accelerated breakdown in thin oxide films due to interfacial stress and carrier depletion,” Material Research Society  spring meeting, 1996.