Conference Publications of Navakanta Bhat
 
  1. N. Bhat and C. Venkatesh, “Impact of Beam Dimensions on Torsional Varactor”, Invited paper at International Conference on Advanced Materials (ICAM), IUMRS 2007
  2. P.R.Kumar, C.Venkatesh, R.Pratap and N. Bhat, “C-V Characterization of a MEMS Torsional Varactor”, International Conference on Advanced Materials (ICAM), IUMRS 2007
  3. Harish, BP and Bhat, Navakanta and Patil, Mahesh B, "Process Variation Aware Estimation of Static Leakage Power in Nano-CMOS", SISPAD 2007.
  4. Satyam Dwivedi, Bharadwaj Amrutur, Navakanta Bhat, "Optimizing Resolution of Signals in a Low IF Receiver", IEEE ISSCS 2007.
  5. Harish, BP and Bhat, Navakanta and Patil, Mahesh B, " CV based Analytical Modeling of Dynamic Power for 65-nm CMOS Library Characterization", IEEE VLSI Design and Test Symposium 2007.
  6. Harish, BP and Bhat, Navakanta and Patil, Mahesh B, "Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs", International Conference on Computing: Theory and Applications, 2007.
  7. G.C. Deepak, Navakanta Bhat, and S.A. Shivashankar, "Structural and Electrical Properties of Er2O3 Thin Films Deposited by RF Sputtering for Gate Dielectric Applications", E1-0586, 211th ECS Meeting, Chicago, May 2007
  8. C.Venkatesh and Navakanta Bhat, "Reliability of torsional varactor", International Symposium on physical and failure analysis of Integrated Circuits, July 2007.
  9. Balaji Jayaraman and Navakanta Bhat, “High precision 16-bit readout gas sensor interface in 0.13ěm CMOS,” International Symposium on Circuits and Systems, pp. 3071 – 3074, May 2007
  10. K. Sivaramakrishna, K. Jayant and N. Bhat, “A Novel CMOS Compatible Three Terminal 3D Tunable Micro Inductor”, IEEE VLSI Design and Test Symposium, 2006
  11. S. Jayaram and N. Bhat, “Integrated Stability Analysis Methods for Hybrid Systems”, IEEE VLSI Design and Test Symposium, 2006
  12. S. Bagga, N. Bhat and S. Mohan, “Gas Sensor Interface ASIC on 0.7m CMOS Technology”, IEEE VLSI Design and Test Symposium, 2006
  13. K. Sandeep, C. Kshirasagar and N. Bhat, “General Purpose Capacitive Sensing Circuit using Correlated Double sampling”, IEEE VLSI Design and Test Symposium, 2006
  14. Balaji Jayaraman and Navakanta Bhat, “System Level Modeling and Simulation of a Gas Sensor Interface”, IMAPS India National Conference, 2006
  15. B.P. Harish and Navakanta Bhat, “Resistive Modeling of Estimation of Static Leakage Power in Nanoscale CMOS”, IMAPS India National Conference, 2006
  16. S.Bagga, S.Mohan and N.Bhat," Effect of the Sensor Film Thickness on the Sensitivity of the Tin Oxide based LPG Gas Sensor" in proceedings of the Conference on Smart Structures and MEMS System for Aerospace Applications, December 1-2,2006, Hyderabad, India.
  17. S.Bagga, S.Mohan and N.Bhat," Influence of Substrate Temperature on the Optical and Structure Properties of Tin Oxide Films" in National Symposium on Instrumentation, October 12-15, 2006, Gwalior, India.
  18. Balaji Jayaraman and Navakanta Bhat, “A Temperature Independent Current Source on 0.13µm CMOS Technology”, International Conference on Computers and Devices for Communication (CODEC), 2006
  19. K. Jayant, Hithesh Gatty and Navakanta Bhat, “A novel low actuation Voltage switch using the concept of displacement amplification”, Indo-Chinese Workshop on MEMS, 2006
  20. C. Kshirasagar, A. Madan, N.Bhat, “Device Performance Variations in 20nm Trigate FinFET”, International Workshop on Physics of Semiconductor Devices, December 2005
  21. C. Venkatesh, K.J.Vinoy and N. Bhat, “Application of Torsional Varactor in the design of phase shifters” International Conference on MEMS and Semiconductor Nanotechnology, IIT Kharagpur, December 2005
  22. N. Bhat, S. Rajesh, S. Syamala, “ASIC Interface design for MEMS Gyroscope Sensor”, Invited paper at the National Symposium on Instrumentation, CUSAT, Cochin, November 2005
  23. C. Venkatesh, and N. Bhat, “Issues in design of torsional MEMS varactor”, Invited paper at ISSS Conference, Bangalore, July 2005.
  24. S. Rajesh, S. Syamala, N. Bhat, “Novel Test Structure to Emulate Capacitance Variations of a Rate-Grade Gyroscope”. Asian Solid State Cicruit Conference, Taiwan, November 2005
  25. N. Bhat, “SOC Technology : CMOS and Beyond”, Invited tutorial at the Asia South Pacific International Conference on Embedded Systems”, July 2005
  26. R. Srinivasan and N. Bhat, “Impact of channel engineering on unity gain frequency and noise figure in 90nm NMOS transistor for RF application”, 18th International VLSI Design Conference, Calcutta , January 2005.
  27. R. Srinivasan and N. Bhat, “Impact of Gate-Drain/Source Overlap on Noise Figure in 90nm NMOS Transistor for RF Applications”, International Symposium on Microwaves, 2004
  28. B.P.Harish, N. Bhat, “Characterization of 65nm CMOS NAND gate delay sensitivity on gate length and implant dose variations”, IINC 2004
  29. J.P.Kulkarni, N.Bhat, “Improving Tuning Range in Varactors using Poly-Silicon depletion Effect”, Asia Pacific Microwave Conference, New Delhi, 2004
  30. C. Venkatesh and N. Bhat, “A MEMS Oscillator based on Displacement Sensing Principle”, 8th IEEE VLSI Design and Test Workshops 2004
  31. B.P.Harish, R.Srinivasan and N. Bhat, “Process Sensitivity Evaluation of 90nm CMOS Technology with Gate to Source/Drain Overlap Length as a Device Design Parameter”, 8th IEEE VLSI Design and Test Workshops 2004
  32. R. Sangati, S. Syamala and N. Bhat, “Capacitance Sensing Techniques for MEMS Gyroscope”, 8th IEEE VLSI Design and Test Workshops 2004
  33. R. Srinivasan and N. Bhat, “Reassessment of Channel Engineering in sub-100nm MOSFETs”, 8th IEEE VLSI Design and Test Workshops 2004
  34. H C Srinivasaiah and N. Bhat, “Response Surface Modeling of 100nm CMOS Process Technology Using Design of Experiment”", 17th International VLSI Design Conference, 2004, Bombay
  35. S Jairam, N. Bhat, S. S. Bisht, R. Pratap,  “A Quasi Static Model for a Simply Supported Beam in a Circuit Simulation Framework”, 17th International VLSI Design Conference, 2004, Bombay
  36. M.P.Singh, G.C.Deepak, N. Bhat and S.A.Shivashankar, “Electrical Characterization of Gd2O3  Deposited by Low Pressure Metalorganic Chemical Vapour Deposition” INAE Conference on Nanotechnology, Chandigarh,  December 2003
  37. N. Bhat and S. Pamidighantam, “MEMS and Applications”, Tutorial at IEEE TENCON 2003, October 2003, Bangalore
  38. N. Bhat, C. Venkatesh and S. Pati, “Micro Electro Mechanical Systems (MEMS): An Overview”, Tutorial at 7th IEEE VLSI Design and Test Workshops 2003, Bangalore
  39. A. K. Gupta and N. Bhat, “A Low Power Circuit to Generate Neuron Activation Function and its Derivative using Back Gate Effect”, 7th IEEE VLSI Design and Test Workshops 2003, Bangalore
  40. S. Deb and N. Bhat, “Design and Implementation of Passive RF Tag IC”, 7th IEEE VLSI Design and Test Workshops 2003, Bangalore
  41. C.S.Thakur and N. Bhat, “Impact of Gate to Source/Drain Overlap for Analog CMOS Circuit Application in sub-100nm Technology”, 7th IEEE VLSI Design and Test Workshops 2003, Bangalore
  42. N. Bhat and S. Pamidighantam, “MEMS and Applications”, Tutorial at IEEE TENCON 2003, Bangalore
  43. M.P.Singh, C.S.Thakur, K.Shalini, T. Shripathi, N. Bhat and S.A.Shivashankar, “ A Comparative Study of Erbium Oxide and Gadolinium Oxide High-K Dielectric Thin Films Grown by Low Pressure Metalorganic Chemical Vapour Deposition (MOCVD) Using b-Diketonates as Precursors”, 204th Meeting of Electrochemical Society, USA 2003
  44. G.C.Deepak, M.S.Dharmapraksh, N. Bhat and S.A.Shivashankar, “Electrical Characterization of MOCVD grown HfO2 Thin Films for Gate Dielectric Applications”, 12th International Workshop on Physics of Semiconductor Devices, Chennai, 2003
  45. A. K. Pugalia, J.P. Kulkarni, N. Bhargava and N. Bhat, “Single Pocket Halo Sensitivity in 100nm Ananlog Transistor Design”, 12th International Workshop on Physics of Semiconductor Devices, Chennai, pp. 603-605, 2003
  46. A. Kumar, R. Pratap and N. Bhat, “Modeling and Simulation of Thermalization Profile of Sputtered Atoms in a Glow Discharge Cell”, 12th International Workshop on Physics of Semiconductor Devices, Chennai, pp. 564-566, 2003
  47. R Srinivasan and N. Bhat, “Effect of Scaling on the Non-Quasi-Static Behaviour of the MOSFET for RF IC's, 16th International VLSI Design Conference 2003, New Delhi.
  48. M.P. Singh, C.S. Thakur, K. Shalini, N. Bhat and S.A. Shivashankar, Characterization of a Potential Gate Dielectric: MOCVD Grown Erbium Oxide on Silicon,  Electro Chemical Society  Conference, Paris,  2003
  49. C. Venkatesh, S. Pati and N. Bhat, “Torsional MEMS Varactor with Low Actuation Voltage” 2nd International Conference on Materials for Advanced Technologies, Singapore 2003
  50. S. Pati, C. Venkatesh, N. Bhat and R. Pratap, “Voltage Controlled Oscillator Using Tunable MEMS Resonator”, 2nd International Conference on Materials for Advanced Technologies, Singapore 2003
  51. H C Srinivasaiah and N. Bhat, “Implant dose sensitivity of 0.1mm CMOS inverter delay", 7th ASPDAC / 15th International VLSI Design Conference, 2002, Bangalore
  52. H C Srinivasaiah and N. Bhat  "Statistical modelling of 0.1mm NMOS device characteristics for implant dose variations", 6th IEEE VLSI Design & Test workshop-2002, Bangalore
  53. K. Maitra and N. Bhat, "Poly-reoxidation Process Step for Suppressing Edge Direct Tunneling (EDT) Through Ultrathin Gate Oxides in NMOSFETs", 6th IEEE VLSI Design & Test workshop-2002
  54. P K Saxena and N. Bhat, "Single Event Upset Response of a 0.09mm SRAM cell using 2D and 3D simulation", 6th IEEE VLSI Design & Test workshop-2002, Bangalore
  55. R Srinivasan, C Venkatesh and N. Bhat, "Comparative study of Tuned amplifier performance with different inductor configurations", 6th IEEE VLSI Design & Test workshop-2002, Bangalore
  56. A. Gupta and N. Bhat, "Hardware realisation of a digitally controllable neuron activation function and its derivative for extremely low power applications", 6th IEEE VLSI Design & Test workshop-2002
  57. N. Bhat, “CMOS Technology Issues in Mixed Signal Design” Invited Tutorial, 6th IEEE VLSI Design & Test workshop-2002, Bangalore
  58. M. P. Singh, C. S. Thakur, N. Bhat, and S. A. Shivashankar, “A study of Al2O3:C films on Si(100) grown by low pressure MOCVD”, Material Research Society  fall Meeting USA  2002
  59. H.C.Srinivasaiah and N. Bhat, “Optimization of 0.1mm NMOS Transistor using Disposable Spacer Technique”, 5th IEEE VLSI Design and Test Workshop, 2001
  60. Simi E., Sudheer S.S. and  N. Bhat, “Dual Vt Technology using Dual Thickness Gate Oxide”,  5th IEEE VLSI Design and Test Workshop, 2001
  61. H C Srinivasaiah and N. Bhat, "Simulation Study of Implant Dose Sensitivity of a 0.1 mm NMOSFET", 11th International Workshop on "The Physics  of Semiconductors” 2001
  62. N. Bhat, “Circuit and Process Perspectives for the Transistor Design in the Deep Sub-micron Technology”, Invited talk at the National seminar on VLSI: Systems, Design and Technology, 2000
  63. N. Bhat, P. Chen, P. Tsui, A. Das, M. Foisy, Y. Shiho, J. Higman, J-Y Nguyen, S. Gonzales, S. Collins, D. Workman, “Hot carrier reliability considerations in the integration of dual gate oxide transistor process on a sub-0.25µm technology for embedded applications,” International Electron Device Meeting, 1998.
  64. N. Bhat, H. Chuang, P. Tsui, R. Woodruff, J. Grant, R. Kruth, A. H. Perera, S. Poon, S. Collins, D. Dyer, V. Misra, I. Yang, S. Venkatesan, P. V. Gilbert, “Performance, standby power, and manufacturability trade-off in transistor design consideration for 0.25-µm technology,” SPIE Microelectronics Device Technology conference, 1998.
  65. N. Bhat, A. Wang and K.C. Saraswat, “Effect of annealing ambient on performance and reliability of LPCVD oxides for TFTs,” Material Research Society  spring meeting, 1996.
  66. N. Bhat, M.Cao and K.C.Saraswat, “Bias temperature instability in hydrogenated polysilicon thin film transistors,” Society for Information Display conference ,  1995.
  67. N. Bhat and K.C.Saraswat, “Interface-state generation in deposited oxides due to bias temperature stress,” Electrochemical Society extended abstracts, 1994.
  68. N. Bhat and K.C.Saraswat, “Degradation of LPCVD oxides,” International Display Research conference, 1994.
  69. H. Oi, Y. Shiho, P. Chen, N. Bhat, “Dual Gate Oxide Process Integration for High Performance Embedded Memory Products”,  Solid state Device Meeting, 1998
  70. T.C.Yang, N.Bhat, and K.C. Saraswat, “Effect of interface stress on reliability of gate oxide,” 4th Symposium on Silicon nitride and silicon oxide thin insulating films. 191st meeting of the ECS, May 1997  (invited paper).
  71. V. Subramanian, N. Bhat, and K.C.Saraswat, “Accelerated breakdown in thin oxide films due to interfacial stress and carrier depletion,” Material Research Society  spring meeting, 1996.