Work done at Motorola

0.25µm technology development and transfer: Designed and developed  a  high performance transistor process with  the transistor gate length down to  0.16µm. Successfully transferred the process to manufacturing which enabled the production of  state of the art RISC microprocessor (PowerPC 604e) running at frequency exceeding 350Mhz.  Operated in a cross functional team involving members from design/process/device/manufacturing groups. Also initiated the process development and integration of multilevel Aluminum metal interconnect and tungsten via reliability for the 0.25µm technology. (1997)
Dual gate oxide technology development: Successfully co-developed the enabling technology to integrate two different thickness of gate oxides (one typically less than 4 nm and the other typically greater than 7 nm) in a single chip. Scaling the MOS transistors in the sub 0.25 µm regime poses a challenge in interfacing low voltage transistors (typically less than 1.8V) in the core of the circuit such as a microprocessor to the higher voltage (typically more than 3.3V) requirement of external bus.  Hence it becomes desirable to integrate two different gate oxide thickness in the same chip.  Carefully conducted research on  reliable process options using analytical characterization as well as electrical characterization of capacitors and transistors.  The process integration, that was developed as a result of this effort, is used in several products.  (1998)
 sub-0.1µm transistor development: Development of MOS transistors with gate lengths below 0.1µm. The goal of this project was to design and develop manufacturable MOS transistors with gate lengths down to 0.06µm for the Giga Hertz Microprocessor. (1999)

Investigated the reliability of multilevel metal interconnects for submicron technology. Characterized the via failure and studied impact of via layout on the failure. Jointly developed a robust test vehicle  to monitor the via reliability. (1995)

Characterized thin film transistors for high density static RAMs. Developed the charge pumping technique and studied the process induced damage on Si-SiO2 interface in MOS transistors. (1994)